The converter described in that patent application is shown, by way of example, in accompanying FIG. 1. It essentially comprises, between a voltage source SE and a current source C, a succession of controllable switching cells CL1, CL2, . . . , CLn, each having two switches T1, T'1; T2, T'2; . . . ; Tn, T'n, with one pole of each of the two switches forming part of a pair of upstream poles and the other pole of each of the switches forming part of a pair of downstream poles, the pair of downstream poles of an upstream cell being connected to the pair of upstream poles of a downstream cell, and the pair of upstream poles of a first cell CL1 being connected to said current source C, while the pair of downstream poles of a last cell CLn is connected to said voltage source SE, the converter also comprising a respective capacitor C1, C2, . . . , Cn for each cell, each capacitor being connected between the two poles constituting the pair of downstream poles of its cell, the converter further having control means (not shown) governing the nominal operation of the converter and acting on the switches of the successive cells in such a manner that the two switches of any one cell are always in respective opposite conduction states (represented by control links such as lc1), such that in response to a cell control signal delivered by said control means, one of the two switches in a given cell is successively in a first conduction state and then in a second conduction state during a cyclically repeated converter period, and such that in response to cell control signals that are identical but offset in time by a fraction of said converter period, the switches of successive cells function respectively in the same manner but offset in time by said fraction of a period.
Preferably, said fraction of a period is equal to the reciprocal of the number n of cells, i.e. 2.pi./n, which is optimal with respect to harmonics generated on the output and which enables the voltages charged on the capacitors of the converter to be balanced naturally. Some other offset is nevertheless conceivable.
In such a converter, the successive capacitors C1, C2, . . . , Cn have respective increasing mean charge voltages, the mean charge voltage of the capacitor associated with each of said cells being equal to the product of a voltage VE delivered by said voltage source SE multiplied by the reciprocal of the number of cells in the converter and by the rank of the cell, i.e. VE/3, 2VE/3, VE when n=3, i.e. when the converter has only three cells.
The term "multilevel converter" is used below to designate a converter that satisfies the above description.
The advantage of such a converter is that, under normal operating conditions, each of said switches bears only a fraction of the maximum voltage to which the converter is subjected, i.e. the fraction that corresponds to the difference between the voltages charged on two capacitors of two adjacent cells. Thus, for the switches, it is possible to use components that are less costly and/or faster. If faster components are used, a converter can be made whose operating frequency is higher, which is very advantageous in practice.
In the above description, the inductance of the circuits is not mentioned. In addition, the modular appearance of the converter would encourage the person skilled in the art to implement it in the form of a modular structure, each structural unit corresponding to a respective cell, and containing the two switches of the cell and the cell capacitor connected between the downstream poles of the switches.
Unfortunately, experience has shown that such structural implementations do not satisfy expectations. The inventors have established that transient voltage surges increasing the voltages to be withstood by the switches are caused by the inductance of the conductors between the units of such a modular structure.